1. Field of the Invention
The present invention relates to a memory row architecture having memory row redundancy repair function, and more particularly, to a memory row architecture having memory row redundancy repair function that implements a redundancy memory section in one side of each normal memory section.
2. Description of the Prior Art
In general, the conventional memory row architecture includes a so-called redundancy memory section besides a plurality of normal memory sections nowadays, wherein structure of the redundancy memory section is similar to that of the normal memory section, and the redundancy memory section is utilized for replacing memory units of the plurality of normal memory sections that are considered to be failed.
Please refer to FIG. 1. FIG. 1 shows a simplified block diagram of a memory row architecture 100 having memory row redundancy repair function according to a prior art. As shown in FIG. 1, the memory row architecture 100 includes a first normal memory section 111, a second normal memory section 112, a third normal memory section 113, a fourth normal memory section 114, a fifth normal memory section 115, a sixth normal memory section 116, a seventh normal memory section 117, an eighth normal memory section 118, a first redundancy memory section 121, and a second redundancy memory section 122, wherein the first redundancy memory section 121 is coupled to the first normal memory section 111 and the second redundancy memory section 122 is coupled to the eighth normal memory section 118. In addition, the first redundancy memory section 121 and the first normal memory section 111, the second normal memory section 112, the third normal memory section 113, and the fourth normal memory section 114 are coupled to each other so as to make up a first memory row redundancy repair module. When any normal memory section included in the above first memory row redundancy repair module is considered to be failed, the first memory row redundancy repair module utilizes the first redundancy memory section 121 to repair the failed normal memory sections. Similarly, the second redundancy memory section 122 and the eighth normal memory section 118, the fifth normal memory section 115, the sixth normal memory section 116, and the seventh normal memory section 117 are coupled to each other so as to make up a second memory row redundancy repair module. When any normal memory section included in the above second memory row redundancy repair module is considered to be failed, the second memory row redundancy repair module utilizes the second redundancy memory section 122 to repair the failed normal memory section.
However, since small signals of the first normal memory section 111 and the eighth normal memory section 118 will become smaller due to adding the first redundancy memory section 121 and the second redundancy memory section 122, the small signals of the first normal memory section 111 and the eighth normal memory section 118 will be different from small signals of the second normal memory section 112, the third normal memory section 113, the fourth normal memory section 114, the fifth normal memory section 115, the sixth normal memory section 116, the seventh normal memory section 117. This result is possible to bring down electrical performance and efficiency of the whole memory row architecture 100.